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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT154 4-to-16 line decoder/demultiplexer
Product specification File under Integrated Circuits, IC06 September 1993

PhilipsSemiconductors

Product specification

4-to-16 line decoder/demultiplexer
FEATURES • 16-line demultiplexing capability • Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs • 2-input enable gate for strobing or expansion • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low powerSchottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

74HC/HCT154
The 74HC/HCT154 decoders accept four active HIGH binary address inputs and provide 16 mutually exclusive active LOW outputs. The 2-input enable gate can be used to strobe the decoder to eliminate the normal decoding “glitches” on the outputs, orit can be used for the expansion of the decoder. The enable gate has two AND’ed inputs which must be LOW to enable the outputs. The “154” can be used as a 1-to-16 demultiplexer by using one of the enable inputs as the multiplexed data input. When the other enable is LOW, the addressed output will follow the state of the applied data.

TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used todetermine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS LogicPackage Information”. PARAMETER propagation delay An, En to Yn input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 3.5 60 HCT 13 3.5 60 ns pF pF UNIT

September 1993

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Philips Semiconductors

Product specification

4-to-16 line decoder/demultiplexer
PIN DESCRIPTION PIN NO. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17 18,19 12 23, 22, 21, 20 24 SYMBOL Y0 to Y15 E0, E1 GND A0 to A3 VCC

74HC/HCT154

NAME AND FUNCTION outputs (active LOW) enable inputs (active LOW) ground (0 V) address inputs positive supply voltage

(a)

(b)

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

Fig.4 Functional diagram.

September 1993

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Philips Semiconductors

Product specification4-to-16 line decoder/demultiplexer
FUNCTION TABLE INPUTS E0 H H L L L L L L L L L L L L L L L L L Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care E1 H L H L L L L L L L L L L L L L L L L A0 X X X L H L H L H L H L H L H L H L H A1 X X X L L H H L L H H L L H H L L H H A2 X X X L L L L H H H H L L L L H H H H A3 X X X L L L L L L L L H H H H H H H H Y0 H H H L H H H H H H H H HH H H H H H Y1 H H H H L H H H H H H H H H H H H H H Y2 H H H H H L H H H H H H H H H H H H H Y3 H H H H H H L H H H H H H H H H H H H Y4 H H H H H H H L H H H H H H H H H H H Y5 H H H H H H H H L H H H H H H H H H H Y6 H H H H H H H H H L H H H H H H H H H OUTPUTS Y7 H H H H H H H H H H L H H H H H H H H Y8 H H H H H H H H H H H L H H H H H H H Y9 H H H H H H H H H H H H L H H H H H H74HC/HCT154

Y10 Y11 Y12 Y13 Y14 Y15 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L

Fig.5 Logic diagram.

September 1993

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Philips Semiconductors

Product specification

4-to-16 line decoder/demultiplexer
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